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RTL/Logics Design Engineer

B.E/B.Tech, M.S/M.Tech with 2-10 years of experience. Expertise in micro-architecture, design of design blocks (IP) to system-on-chip (SoC) components.

Experience experience: "2-10 years "

ASIC Verification Engineer

BE/B.Tech, with 2-10 years of experience or MTech with 1+ Experience. Develop verification testbench components for chip/module level using System Verilog, C & Perl

Experience 2 years

Python Developer

Required python developer for Automotive domain

Experience Experience: 2+ years


SoC based IP Design

RTL Design Knowledge, Digital Logics and Verilog.

IoT design

C programming, 32bit Microcontroller Knowledge and TCP/IP